The 41st IPP Symposium
Can Mainstream Processors Support Hardware Transactional Memory?
David Christie, AMD
While Hardware Transactional Memory concepts have been around for more than a decade, actual implementation in any high-volume commercial microprocessor has been a chicken-and-egg problem -- HTM poses enough complexity for the hardware that some serious justification is needed, yet it's been difficult to demonstrate the potential benefit on real applications due to modeling and application development limitations. On top of that, there are many places the line can be drawn between software and hardware, and finding a sweet spot is difficult without knowing how TM applications will tend to behave. Yet another dimension is added by the need for commonality in the software development infrastructure to support portability. This talk will cover some of the difficulties in providing HTM support, and what a best-effort approach might look like for the x86 architecture.
Bio: Dave Christie is a Fellow in AMD's Research and Advanced Development Lab, where he leads instruction set development and performance analysis efforts. He helped initiate independent x86 processor design at AMD in the early '90s, was co-architect of the AMD64 instruction set, and has over 50 patents in the area of computer architecture.
