Addressing Undifferentiated Nanowires

• Nanowire Addressing with Randomized-Contact Decoders by Eric Rachlin and John E. Savage, Procs. IEEI/ACM Int. Conf. on Computer-Aided Desing (ICCAD), , 2006.
  Abstract Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD) [11], for example, field-effect transistors are randomly created at about half of the NW/MW junctions.
  In this paper, we tightly bound the number of MWs required to produce a correctly functioning RCD with high probability. We show that the number of MWs is logarithmic in the number of NWs, even when errors occur. We also analyze the overhead associated with controlling a stochastically assembled decoder. As we explain, lithographically-produced control circuitry must store information regarding whichMWs control which NWs. This requires more area than the MWs themselves, but has received little attention elsewhere.

Survey Article

• Nanowire-Based Programmable Architectures by Andre' DeHon ACM J. on Emerging Technologies in Computing Systems, Vol. 1, No. 2, pp. 109–162, (2005)
  ,
  Abstract Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

Errors in Crossbars

• Nanowire-Based Programmable Architectures by Helia Naeimi and André DeHon Proceedings of the International Conference on Field-Programmable Technology (ICFPT2004) pp. 49-56, December 6-8, (2004)
  ,
  Abstract Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic Programmable Logic Arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design as this scale. We introduce a strategy for tolerating defective crosspoints and develop a lineartime, greedy algorithm for mapping PLA logic around crosspoint defects. We note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%.

• Addressing in the Face of Uncertainty, by Eric Rachlin and John E Savage Proceedings of the IEEE 2006 Int. Symp. on VLSI , pp. 225-230, March 2-3, 2006.
  ,
  Abstract Exploiting the high-potential of nanoscale architectures requires that they be controlled by CMOS technology. Such an interface, a decoder, must control many nanowires (NWs) with a small number of meso-scale wires (MWs). Multiple types of decoder have been proposed, each of which can be modelled as embedding resistive switches in NWs. In this paper we present a general model for NW decoders and use it to specify the criteria they must meet to function correctly and be fault-tolerant. To illustrate the power of our model, we derive the first bounds on the size of a fault-tolerant randomized contact decoder.